The present disclosure relates to linear regulators. FIG. 1 illustrates a prior art linear regulator 100. The regulator 100 includes a preamplifier stage 102 and an output stage 104. The preamplifier stage 102 includes a preamplifier 106, which may include a set of discrete components, or may be realized as a fully integrated circuit. An input signal is provided to an input terminal 101 of the preamplifier 106. The output of the preamplifier 106 is provided to a pair of discrete power transistors 108, 110 arranged in a push-pull configuration. The proper bias (dc operating point) of transistors 108, 110 is provided by a pair of regulated voltage generating circuits 114, 116. The voltage generated by the circuits 114, 116 is selected to cancel the non-active input voltage region of the transistors 108, 110 at low input voltage levels. The transistors 108, 110 are of opposite types. Transistor 108 is an n-type power Field Effect Transistor (FET) or an npn-type power bipolar transistor, while transistor 110 is a p-type power FET or a pnp-type power bipolar transistor. An output terminal 103 is provided at the junction between transistor 108 and the transistor 110. A feedback line 112 provides a feedback signal to the preamplifier 106, causing it to amplify the difference between the input and output voltages. When the output voltage of the preamplifier 106 is below the input voltage, the output of the preamplifier 106 goes up and the transistor 108 is biased on, sourcing current to any load present at the output terminal 103 and bringing the output voltage to the desired level. The transistor 110 is in cut-off. When the output voltage of the preamplifier 106 is above the input voltage, the output of the preamplifier 106 goes down and the transistor 110 is biased on, sinking current from any load present at the output terminal 103 and thus bringing the output voltage to the desired level. The transistor 108 is in cut-off.